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? semiconductor components industries, llc, 2015 october, 2015 ? rev. 1 1 publication order number: kae?02150/d kae-02150 1920 (h) x 1080 (v) interline ccd image sensor the kae?02150 image sensor is a 1080p (1920 1080) ccd in a 2/3 optical format that provides exceptional imaging performance in extreme low light applications. each of the sensor?s four outputs incorporate both a conventional horizontal ccd register and a high gain emccd register. an intra-scene switchable gain feature samples each charge packet on a pixel-by-pixel basis . this enables the camera system to determine whether the charge will be routed through the normal gain output or the emccd output based on a user selectable threshold. this feature enables imaging in extreme low light, even when bright objects are within a dark scene, allowing a single camera to capture quality images from sunlight to starlight. this image sensor is based on the 5.5-micron interline transfer ccd platform, and features extended dynamic range, excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs. a vertical overflow drain structure suppresses image blooming, provides excellent mtf, and enables electronic shuttering for precise exposure control. table 1. general specifications parameter typical value architecture interline ccd; with emccd total number of pixels 2004 (h) 1144 (v) number of effective pixels 1960 (h) 1120 (v) number of active pixels 1920 (h) 1080 (v) pixel size 5.5 m (h) 5.5 m (v) active image size 10.56 mm (h) 5.94 mm (v) 12.1 mm (diag.), 2/3 optical format aspect ratio 16:9 number of outputs 1, 2, or 4 charge capacity 20,000 e ? output sensitivity 44 v/e ? quantum efficiency mono / color (rgb) 50% / 33%, 41%, 43% read noise (20 mhz) normal mode (1 gain) intra-scene mode (20 gain) 9e ? rms < 1 e ? rms dark current (0 c) photodiode, vccd < 0.1 e ? /s, 6 e ? /s dynamic range normal mode (1 gain) intra-scene mode (20 gain) 68 db 86 db charge transfer efficiency 0.999999 blooming suppression > 1000 x smear ?100 db image lag < 1 e ? maximum pixel clock speed 40 mhz maximum frame rate normal mode, intra-scene mode 60 fps (40 mhz), 30 fps (20 mhz) package 135 pin pga cover glass clear glass, taped note: all parameters are specified at t = 0 c unless otherwise noted. www.onsemi.com see detailed ordering and shipping information on page 2 o f this data sheet. ordering information features ? intra-scene switchable gain ? wide dynamic range ? low noise architecture ? exceptional low light imaging ? global shutter ? excellent image uniformity and mtf ? bayer color pattern and monochrome applications ? surveillance ? scientific imaging ? medical imaging ? intelligent transportation figure 1. kae?02150 interline ccd image sensor
kae?02150 www.onsemi.com 2 ordering information us export controls apply to all shipments of this product designated for destinations outside of the us and canada, requiring on semiconductor to obtain an export license from the us department of commerce before image sensors or evaluation kits can be exported. table 2. ordering information part number description marking code kae?02150?abb?jp?fa monochrome, microlens, pga package, taped clear cover glass (no coatings), standard grade kae?02150?abb serial number kae?02150?abb?jp?ee monochrome, microlens, pga package, taped clear cover glass (no coatings), engineering grade kae?02150?fbb?jp?fa color (bayer rgb), microlens, pga package, taped clear cover glass (no coatings), standard grade kae?02150?fbb serial number kae?02150?fbb?jp?ee color (bayer rgb), microlens, pga package, taped clear cover glass (no coatings), engineering grade table 3. evaluation support part number description kae?02150?ab?a?gevk kae?02150 evaluation kit lens?mount?kit?c?gevk lens mount kit for it?ccd evaluation hardware see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com .
kae?02150 www.onsemi.com 3 device description architecture figure 2. block diagram 8 8 8 8 24 24 14 14 960 8 24 10 1 28 1 4 2070 960 8 24 10 1 28 1 4 960 8 24 10 1 28 1 4 2072 2072 2072 960 8 24 10 1 28 1 4 2070 2072 vout c3 vout d3 vout a3 vout b3 vout c1 vout d1 vout c2 vout d2 vout a1 vout b1 vout a2 vout b2 1920 1080 5.5 m pixels dark reference pixels there are 14 dark reference rows at the top and bottom of the image sensor, as well as 24 dark reference columns on the left and right sides. however, the rows and columns at the very edges should not be included in acquiring a dark reference signal, since they may be subject to some light leakage. active buffer pixels 8 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. these pixels are light sensitive but are not tested for defects and non-uniformities. image acquisition an electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at each photo-site. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. when the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming esd protection adherence to the power-up and power-down sequence is critical. failure to follow the proper power-up and power-down sequences may cause damage to the sensor. see power-up and power-down sequence section.
kae?02150 www.onsemi.com 4 bayer color filter pattern figure 3. bayer color filter pattern 8 8 8 8 24 24 14 14 960 8 24 10 1 28 1 4 2070 960 8 24 10 1 28 1 4 960 8 24 10 1 28 1 4 2072 2072 2072 960 8 24 10 1 28 1 4 2070 2072 vout c3 vout d3 vout a3 vout b3 vout c1 vout d1 vout c2 vout d2 vout a1 vout b1 vout a2 vout b2 1920 1080 5.5 m pixels
kae?02150 www.onsemi.com 5 physical description pin grid array and pin description figure 4. pga package designations (bottom view) h g f e d c b a 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 table 4. pin description pin label description a02 v3b vccd bottom phase 3 a03 n/c no connection a04 rg2a amplifier 2 reset, quadrant a a05 n/c no connection a06 vdd23ab amplifier 2 and 3 supply, quadrants a, b a07 h1bema emccd barrier phase 1, quadrant a a08 h2ba hccd barrier phase 2, quadrant a a09 gnd ground a10 h2bb hccd barrier phase 2, quadrant b a11 h1bemb emccd barrier phase 1, quadrant b a12 vdd23ab amplifier 2 and 3 supply, quadrants a, b a13 n/c no connection a14 rg2a amplifier 2 reset, quadrant b a15 n/c no connection a16 v3b vccd bottom phase 3 a17 esd esd protection disable b01 devid device id resistor b02 v4b vccd bottom phase 4 b03 vout1a amplifier 1 output, quadrant a
kae?02150 www.onsemi.com 6 table 4. pin description (continued) pin description label b04 vout2a video output 2, quadrant a b05 h2sw3a hccd output 3 selector, quadrant a b06 vout3a video output 3, quadrant a b07 h2bema emccd barrier phase 2, quadrant a b08 h1ba hccd barrier phase 1, quadrant a b09 gnd ground b10 h1bb hccd barrier phase 1, quadrant b b11 h2bemb emccd barrier phase 2, quadrant b b12 vout3b video output 3, quadrant b b13 h2sw3b hccd output 3 selector, quadrant b b14 vout2b video output 2, quadrant b b15 vout1b amplifier 1 output, quadrant b b16 v4b vccd bottom phase 4 b17 sub substrate c01 v1b vccd bottom phase 1 c02 n/c no connection c03 vss1a amplifier 1 return, quadrant a c04 vdd23ab amplifier 2 and 3 supply, quadrants a, b c05 h2sw2a hccd output 2 selector, quadrant a c06 n/c no connection c07 h1sema emccd storage multiplier phase 1, quadrant a c08 h2sa hccd storage phase 2, quadrant a c09 gnd ground c10 h2sb hccd storage phase 2, quadrant b c11 h1semb emccd storage multiplier phase 1, quadrant b c12 n/c no connection c13 h2sw2b hccd output 2 selector, quadrant b c14 vdd23ab amplifier 2 and 3 supply, quadrants a, b c15 vss1b amplifier 1 return, quadrant b c16 n/c no connection c17 v1b vccd bottom phase 1 d01 v2b vccd bottom phase 2 d02 vdd1a amplifier 1 supply, quadrant a d03 rg1a amplifier 1 reset, quadrant a d04 h2xa floating gate exit hccd gate, quadrant a d05 h2la hccd last gate, outputs 1, 2 and 3, quadrant a d06 rg3a amplifier 3 reset, quadrant a d07 h2sema emccd storage multiplier phase 2, quadrant a d08 h1sa hccd storage phase 1, quadrant a d09 gnd ground d10 h1sb hccd storage phase 1, quadrant b d11 h2semb emccd storage multiplier phase 2, quadrant b d12 rg3b amplifier 3 reset, quadrant b d13 h2lb hccd last gate, outputs 1, 2 and 3, quadrant b d14 h2xb floating gate exit hccd gate, quadrant b
kae?02150 www.onsemi.com 7 table 4. pin description (continued) pin description label d15 rg1b amplifier 1 reset, quadrant b d16 vdd1b amplifier 1 supply, quadrant b d17 v2b vccd bottom phase 2 e01 v2t vccd top phase 2 e02 vdd1c amplifier 1 supply, quadrant c e03 rg1c amplifier 1 reset, quadrant c e04 h2xc floating gate exit hccd gate, quadrant c e05 h2lc hccd last gate, outputs 1, 2 and 3, quadrant c e06 rg3c amplifier 3 reset, quadrant c e07 h2semc emccd storage multiplier phase 2, quadrant c e08 h1sc hccd storage phase 1, quadrant c e09 gnd ground e10 h1sd hccd storage phase 1, quadrant d e11 h2semd emccd storage multiplier phase 2, quadrant d e12 rg3d amplifier 3 reset, quadrant d e13 h2ld hccd last gate, outputs 1, 2 and 3, quadrant d e14 h2xd floating gate exit hccd gate, quadrant d e15 rg1d amplifier 1 reset, quadrant d e16 vdd1d amplifier 1 supply, quadrant d e17 v2t vccd top phase 2 f01 v1t vccd top phase 1 f02 n/c no connection f03 vss1c amplifier 1 return, quadrant c f04 vdd23cd amplifier 2 and 3 supply, quadrants c, d f05 h2sw2c hccd output 2 selector, quadrant c f06 n/c no connection f07 h1semc emccd storage multiplier phase 1, quadrant c f08 h2sc hccd storage phase 2, quadrant c f09 gnd ground f10 h2sd hccd storage phase 2, quadrant d f11 h1semd emccd storage multiplier phase 1, quadrant d f12 n/c no connection f13 h2sw2d hccd output 2 selector, quadrant d f14 vdd23cd amplifier 2 and 3 supply, quadrants c, d f15 vss1d amplifier 1 return, quadrant d f16 n/c no connection f17 v1t vccd top phase 1 g01 esd esd protection disable g02 v4t vccd top phase 4 g03 vout1c amplifier 1 output, quadrant c g04 vout2c video output 2, quadrant c g05 h2sw3c hccd output 3 selector, quadrant c g06 vout3c video output 3, quadrant c g07 h2bemc emccd barrier phase 2, quadrant c g08 h1bc hccd barrier phase 1, quadrant c
kae?02150 www.onsemi.com 8 table 4. pin description (continued) pin description label g09 gnd ground g10 h1bd hccd barrier phase 1, quadrant d g11 h2bemd emccd barrier phase 2, quadrant d g12 vout3d video output 3, quadrant d g13 h2sw3d hccd output 3 selector, quadrant d g14 vout2d video output 2, quadrant d g15 vout1d amplifier 1 output, quadrant d g16 v4t vccd top phase 4 g17 sub substrate h01 td temperature diode sensor h02 v3t vccd top phase 3 h03 n/c no connection h04 rg2c amplifier 2 reset, quadrant c h05 n/c no connection h06 vdd23cd amplifier 2 and 3 supply, quadrants c, d h07 h1bemc emccd barrier phase 1, quadrant c h08 h2bc hccd barrier phase 2, quadrant c h09 gnd ground h10 h2bd hccd barrier phase 2, quadrant d h11 h1bemd emccd barrier phase 1, quadrant d h12 vdd23cd amplifier 2 and 3 supply, quadrants c, d h13 n/c no connection h14 rg2d amplifier 2 reset, quadrant d h15 n/c no connection h16 v3t vccd top phase 3 h17 subref substrate voltage reference
kae?02150 www.onsemi.com 9 imaging performance table 5. typical operational conditions (unless otherwise noted, the imaging performance specifications are measured using the following conditions.) description condition notes light source continuous red, green and blue led illumination 1 operation nominal operating voltages and timing temperature 0 c 1. for monochrome sensor, only green led used. table 6. specifications description symbol min. nom. max. units sampling plan temperature tested at ( c) notes dark field global non-uniformity dsnu ? ? 2.0 mv pp die tbd bright field global non-uniformity ? 2.0 5.0 % rms die tbd 1 bright field global peak to peak non-uniformity prnu ? 5.0 15.0 %pp die tbd 1 bright field center non-uniformity ? 1.0 2.0 % rms die tbd 1 maximum photoresponse nonlinearity (emccd gain = 1) nl ? 2 ? % design 2 maximum gain difference between outputs (emccd gain = 1) g ? 10 ? % design 2 maximum signal error due to nonlinearity differences (emccd gain = 1) nl ? 1 ? % design 2 horizontal ccd charge capacity h ne ? 30 ? ke ? design vertical ccd charge capacity v ne ? 30 ? ke ? design photodiode charge capacity p ne ? 20 ? ke ? die tbd 3 horizontal ccd charge transfer efficiency hcte 0.999995 0.999999 ? die vertical ccd charge transfer efficiency vcte 0.999995 0.999999 ? die photodiode dark current (average) i pd ? 0.1 70 e ? /p/s die 0 vertical ccd dark current ? 6 ? tbd 0 image lag lag ? ? <1 e ? design antiblooming factor x ab 1,000 ? ? design vertical smear (blue light) smr ? ?100 ? db design read noise (emccd gain = 1) n e ? t ? 9 ? e ? rms design 4 read noise (emccd gain = 20) ? <1 ? e ? rms emccd excess noise factor (gain = 20x) ? 1.4 ? design 0
kae?02150 www.onsemi.com 10 table 6. specifications (continued) description notes temperature tested at ( c) sampling plan units max. nom. min. symbol dynamic range (eccd gain = 1) dr ? 68 ? db design 4, 5 dynamic range (high gain) ? 60 ? db dynamic range (intra-scene) ? 86 ? db output amplifier dc offset (vout2, vout3) v odc 8.0 10 12.0 v die tbd output amplifier dc offset (vout1) v odc ?0.5 1.0 2.5 v die output amplifier bandwidth f ?3db ? 250 ? mhz die 6 output amplifier impedance r out ? 140 ? die tbd output amplifier sensitivity (normal output) v/ n ? 44 ? v/e ? design output amplifier sensitivity (floating gate amplifier) v/ n (fg) ? 6 . 2 ? v/e ? design quantum efficiency (peak) monochrome red green blue qe max ? ? ? ? 50% 33% 41% 43% ? ? ? ? % design power 4-output mode (20mhz) (40mhz) 2-output mode (20mhz) (40mhz) 1-output mode (20mhz) (40mhz) ? ? ? ? ? ? 0.8 0.7 0.5 0.5 0.4 0.4 ? ? ? ? ? ? w design 1. per color 2. value is over the range of 10% to 90% of photodiode saturation. 3. the operating value of the substrate reference voltage, v ab , can be read from pin 60. 4. at 40 mhz. 5. uses 20log (p ne / n e?t ). 6. calculated from f ?3db = 1 / 2 ? r out ? c load where c load = 5 pf.
kae?02150 www.onsemi.com 11 typical performance curves quantum efficiency monochrome with microlens figure 5. monochrome qe with microlens quantum efficiency (%) wavelength (nm) 0 10 20 30 40 50 60 300 400 500 600 700 800 900 1,000 color (bayer rgb) with microlens figure 6. color (bayer rgb) qe with microlens quantum efficiency (%) wavelength (nm) 0 5 10 15 20 25 30 35 40 45 350 400 450 500 550 600 650 700 750 800 850 900 950 1,000 red green blue
kae?02150 www.onsemi.com 12 angular response the incident light angle is varied in a plane parallel to the hccd. monochrome with microlens figure 7. monochrome with microlens angle response response angle (deg) 0 10 20 30 40 50 60 70 80 90 100 ?30 ?20 ?10 0 10 20 30 color (bayer rgb) with microlens figure 8. color with microlens angle response response angle (deg) 0 10 20 30 40 50 60 70 80 90 100 ?30 ?20 ?10 0 10 20 30 red green blue
kae?02150 www.onsemi.com 13 frame rates figure 9. frame rates vs. frequency frames/sec frequency (mhz) dual single quad 10 0 15 20 25 30 35 40 10 20 30 40 50 60 70 80
kae?02150 www.onsemi.com 14 defect definitions table 7. defect definitions description threshold/definition maximum number allowed notes major dark field defective bright pixel 10 mv 20 1, 2 major bright field defective dark pixel 12% 20 minor dark field defective bright pixel 5mv 200 cluster defect a group of 2 to 10 contiguous major defective pixels 8 3 column defect a group of more than 10 contiguous major dark defective pixels along a single column or 10 contiguous bright defective pixels along a single column 0 3, 4 1. the thresholds are defined for an operating temperature of 0 c, quad output mode, and a readout rate of 20 mhz. for operation at 22 c, thresholds of 260 mv for major bright pixels and 35 mv for minor bright pixels would give approximately the same numbers of defec ts. 2. for the color device, a bright field defective pixel deviates by 12% with respect to pixels of the same color. 3. column and cluster defects are separated by no less than 2 good pixels in any direction (excluding single pixel defects). 4. low exposure dark column defects are not counted at temperatures above 0 c.
kae?02150 www.onsemi.com 15 operation table 8. absolute maximum ratings (absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. if the level or the condition is exceeded, the device will be degraded and may be damaged. operation at these values will reduce mttf.) description symbol minimum maximum units notes operating temperature t op ?70 4 0 c 1 humidity rh 5 90 % 2 output bias current i out ? 5 ma 3 off-chip load cl ? 10 pf stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. noise performance will degrade at higher temperatures. 2. t = 25 c. excessive humidity will degrade mttf. 3. total for all outputs. maximum current is ?15 ma for each output. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivi ty). table 9. absolute maximum voltage ratings between pins and ground description minimum maximum units notes vdd23ab, vdd23cd ?0.4 17.5 v 1 vout2, vout3 ?0.4 15 v vdd1, vout1 ?0.4 7.0 v v1b, v1t esd ? 0.4 esd + 22 .0 v v2b, v2t, v3b, v3t, v4b, v4t esd ? 0.4 esd + 14.0 v h1s, h1b, h2s, h2b, h1bem, h2bem, h2sl, h2x, h2sw2, h2sw3, rg1, rg2, rg3 ? 0.4 10 v 1 h1sem, h2sem ?0.4 20 v esd ?9.0 0.0 v sub 6.5 40 v 2, 3 1. ? ? denotes a, b, c or d. 2. refer to application note using interline ccd image sensors in high intensity visible lighting conditions. 3. the measured value for vsub ref is a diode drop higher than the recommended minimum vsub bias. power-up and power-down sequence sub and esd power up first, then power up all other biases in any order. no pin may have a voltage less than esd at any time. all hccd pins must be greater than or equal to gnd at all times. the sub ref pin will not become valid until vdd23ab has been powered, therefore the sub voltage cannot be directly derived from the sub ref pin. the sub pin should be at least 4 v before powering up vdd23ab or vdd23cd. table 10. dc bias operating conditions description pins symbol minimum nominal maximum units maximum dc current notes output amplifier return vss1 v ss1 ?8.3 ?8.0 ?7.7 v 4ma output amplifier supply vdd1 v dd1 4.5 5.0 6.0 v 15 ma output amplifier supply vdd23 v dd23 +14.7 +15.0 +15.3 v 37.0 ma 1 ground gnd gnd 0.0 0.0 0.0 v 17.0 ma substrate sub v sub 6.5 vsub ref ? 0.5 vsub ref + 28 v up to 1 ma (determined by photocurrent) 2 esd protection disable esd esd ?8.3 ?8 .0 ?7.7 v 0.25 ma output bias current vout i out 2.0 2.5 5.0 ma 1. vdd bias pins for all four quadrants must be maintained at 15 v during operation. 2. for each image sensor the voltage output on the vsub ref pin is programmed to be one diode drop, 0.5 v, above the nominal sub voltage. the voltage output on vsub ref is unique to each image sensor and may vary from 6.5 to 10.0 v. the output impedance of vsub ref is approximately 100 k. the applied vsub should be one diode drop lower than the vsub ref value measured on the device, when v dd23 is at the specified voltage.
kae?02150 www.onsemi.com 16 ac operating conditions table 11. clock levels pin hccd and rg function low level amplitude low nominal high low nominal high h2b(a,b,c,d) reversible hccd barrier 2 ?0.2 0.0 0.2 3.1 3.3 3.6 h1b(a,b,c,d) reversible hccd barrier 1 ?0.2 0.0 0.2 3.1 3.3 3.6 h2s(a,b,c,d) reversible hccd storage 2 ?0.2 0.0 0.2 3.1 3.3 3.6 h2b(a,b,c,d) reversible hccd storage 1 ?0.2 0.0 0.2 3.1 3.3 3.6 h2sw(2,3)(a,b,c,d) hccd switch 2 and 3 ?0.2 0.0 0.2 3.1 3.3 3.6 h2l(a,b,c,d) hccd last gate ?0.2 0.0 0.2 3.1 3.3 3.6 h2x(a,b,c,d) floating gate exit ?0.2 0.0 0.2 6.0 6.4 6.8 rg1(a,b,c,d) floating gate reset cap 3.1 3.3 3.6 rg(2,3)(a,b,c,d) floating diffusion reset cap 3.1 3.3 3.6 h1bem(a,b,c,d) multiplier barrier 1 ?0.2 0.0 0.2 4.6 5.0 5.4 h2bem(a,b,c,d) multiplier barrier 2 ?0.2 0.0 0.2 4.6 5.0 5.4 h1sem(a,b,c,d) multiplier storage 1 ?0.3 0.0 0.3 7.0 ? 18.0 h2sem(a,b,c,d) multiplier storage 2 ?0.3 0.0 0.3 7.0 ? 18.0 1. hccd operating voltages. there can be no overshoot on any horizontal clock below ?0.4 v: the specified absolute minimum. the h1sem and h2sem clock amplitudes need to be software programmable to adjust the charge multiplier gain . 2. reset clock operation: the rg1, rg2, and rg3 signals must be capacitive coupled into the image sensor with a 0.01 f to 0.1 f capacitor. the reset clock overshoot can be no greater than 0.3 v, as shown in figure 10, below: figure 10. rg clock overshoot 3.1 v minimum 0.3 v maximum clock capacitances pin capacitance (pf) h1sa 76 h1sb 76 h1sc 76 h1sd 76 h2sa 76 h2sb 76 h2sc 76 h2sd 76 pin capacitance (pf) h1ba 39 h1bb 39 h1bc 39 h1bd 39 h2ba 39 h2bb 39 h2bc 39 h2bd 39 pin capacitance (pf) h1bema 56 h1bemb 56 h1bemc 56 h1bemd 56 h2bema 56 h2bemb 56 h2bemc 56 h2bemd 56 pin capacitance (pf) h1sema 66 h1semb 66 h1semc 66 h1semd 66 h2sema 66 h2semb 66 h2semc 66 h2semd 66 note: the capacitances of all other hccd pins is 15 pf or less.
kae?02150 www.onsemi.com 17 figure 11. emccd clock adjustable levels +18 v h1sema h2sema h1semb h2semb h1semc h2semc h1semd h2semd high low 4 output dac a b c d high low high low high low for the emccd clocks, each quadrant must have independently adjustable high levels. all quadrants have a common low level of gnd. the high level adjustments must be software controlled to balance the gain of the four outputs. figure 12. reset clock drivers rg1 3.3 v rg2 rg3 3.3 v 0.01 to 0.1 f 0.01 to 0.1 f 0 to 75 0 to 75 rg1 clock generator rg2,3 clock generator the reset clock drivers must be coupled by capacitors to the image sensor. the capacitors can be anywhere in the range 0.01 to 0.1 f. the damping resistor values would vary between 0 and 75 depending on the layout of the circuit board.
kae?02150 www.onsemi.com 18 table 12. vccd pin function low nominal high v(1,2,3,4)(t,b) vertical ccd clock, low level ?8.0 ?8.0 ?6 v(1,2,3,4)(t,b) vertical ccd clock, mid level ?0.2 0 0.2 v(1)(t,b) vertical ccd clock, high (3 rd ) level 8.5 9.0 12.5 1. the vertical ccd operating voltages. the vccd low level will be ?8.0 v for operating temperatures of 0 c and above. below 0 c the vccd low level should be increased for optimum noise performance . table 13. bias voltages pin function low nominal high esd esd ?8.3 ?8.0 ?7.7 sub (notes 1, 2) electronic shutter vsub ref + 22 ? vsub ref + 28 vdd1(a,b,c,d) floating gate power 4.5 5.0 6.0 vss1(a,b,c,d) floating gate return ?8.3 ?8.0 ?7.7 vdd(2,3)(a,b,c,d) floating diffusion power 14.7 15.0 15.3 vout1(a,b,c,d) floating gate output range ?0.5 1.0 2.5 vout(2,3)(a,b,c,d) floating diffusion output range 8.0 10.0 12.0 1. caution: do not clock the emccd register while the electronic shutter pulse is high. 2. the substrate bias (sub) should normally be kept at v ab , which can be read from pin 60. however, this value was determined from operation at 0 c, and has an approximate temperature dependence of 0.01 v/degree. device identification the device identification pin (devid) may be used to determine which on semiconductor 5.5 micron pixel interline ccd sensor is being used. table 14. device identification description pins symbol minimum nominal maximum units maximum dc current notes device identification devid devid 44,000 50,000 56,000 0.3 ma 1, 2, 3 1. nominal value subject to verification and/or change during release of preliminary specifications. 2. if the device identification is not used, it may be left disconnected. 3. after device identification resistance has been read during camera initialization, it is recommended that the circuit be disa bled to prevent localized heating of the sensor due to current flow through the r_deviceid resistor. recommended circuit figure 13. device identification recommended circuit r_deviceid kae?02150 v1 v2 adc devid gnd r_external
kae?02150 www.onsemi.com 19 theory of operation image acquisition figure 14. illustration of 2 columns and 3 rows of pixels vccd photo diode vccd this image sensor is capable of detecting up to 20,000 electrons with a small signal noise floor of 1 electron all within one image. each 5.5 m square pixel , as shown in figure 14 above , consists of a light sensitive photodiode and a portion of the vertical ccd (vccd). not shown is a microlens positioned above each photodiode to focus light away from the vccd and into the photodiode. each photon incident upon a pixel will generate an electron in the photodiode with a probability equal to the quantum efficiency. the photodiode may be cleared of electrons (electronic shutter) by pulsing the sub pin of the image sensor up to a voltage of 30 v to 40 v (vsub ref + 22 v to vsub ref + 28 v) for a time of at least 1 s. when the sub pin is above 30 v , the photodiode can hold no electrons, and the electrons flow downward into the substrate. when the voltage on sub drops below 30 v, the integration of electrons in the photodiode begins. the hccd clocks should be stopped when the electronic shutter is pulsed, to avoid having the large voltage pulse on sub coupling into the video outputs and altering the emccd gain . it should be noted that there are certain conditions under which the device will have no anti - blooming protection: when the v1t and v1b pins are high, very intense illumination generating electrons in the photodiode will flood directly into the vccd. when the electronic shutter pulse overlaps the v1t and v1b high - level pulse that transfers electrons from the photodiode to the vccd, then photo-electrons will flow to the substrate and not the vccd. this condition may be desirable as a means to obtain very short integration times . the vccd is shielded from light by metal to prevent detection of more photons. for very bright spots of light, some photons may leak through or around the metal light shield and result in electrons being transferred into the vccd. this is called image smear. image readout at the start of image readout, the voltage on the v1t and v1b pins is pulsed from 0 v up to the high level for at least 1 s and back to 0 v, which transfers the electrons from the photodiodes into the vccd. if the vccd is not empty, then the electrons will be added to what is already in the vccd. the vccd is read out one row at a time. during a vccd row transfer, the hccd clocks are stopped. all gates of type h1 stop at the high level and all gates of type h2 stop at the low level. after a vccd row transfer, charge packets of electrons are advanced one pixel at a time towards the output amplifiers by each complimentary clock cycle of the h1 and h2 gates. the charge multiplier has a maximum charge handling capacity (after gain) of 20,000 electrons. this is not the average signal level. it is the maximum signal level. therefore, it is advisable to keep the average signal level at 15,000 electrons or less to accommodate a normal distribution of signal levels. for a charge multiplier gain of 20x, no more than 15,000/20 = 750 electrons should be allowed to enter the charge mult iplier. overfilling the charge multiplier beyond 20,000 electrons will shorten its useful operating lifeti me. in addition, sending signals larger than 180?200 electrons into the emccd will produce images with lower signal-to-noise ratio than if they were read out of the normal floating diffusion output. see application note and9244.
kae?02150 www.onsemi.com 20 to prevent overfilling the charge multiplier , a non-destructive floating gate output amplifier (vout1) is provided on each quadrant of the image sensor as shown in figure 15 . figure 15. the charge transfer patch of one quadrant 1 clock cycle 4 clock cycles 28 clock cycles 2072 clock cycles empty pixels to vout2 vout1 fg charge transfer from the photo-active vccd columns to the charge multiplier and vout3 10 clock cycles 24 clock cycles from the dark vccd columns sw empty pixels 1 clock cycle the non-destructive floating gate output amplifier is able to sense how much charge is present in a charge packet without altering the number of electrons in that charge packet. this type of amplifier has a low charge-to-voltage conversion gain (about 6.2 v/e ? ) and high noise (about 60 electrons), but it is being used only as a threshold detector, and not an imaging detector. even with 60 electrons of noise, it is adequate to determine whether a charge packet is greater than or less than the recommended threshold of 180 electrons. after one row has been transferred from the vccd into the hccd , the hccd clock cycles should begin. after 10 clock cycles , the first dark vccd column pixel will arrive at vout1. after another 24 (34 total) clock cycles , the first photo-active charge packet will arrive at vout1. the transfer sequence of a charge packet through the floating gate amplifier is shown in figure 16 below. the time steps of this sequence are labeled a through d, and are indicated in the timing diagram shown as figure 17. the rg1 gate is pulse high during the time that the h2x gate is pulsed high. this holds the floating gate at a constant voltage so the h2x gate can pull the charge packet out of the floating gate. the rg1 pulse should be at least as wide as the h2x pulse. the h2x pulse width should be at least 12 ns. the rising edge of h2x relative to the falling edge of h1s is critical. the h2x pulse cannot begin its rising edge transition until the h1s edge is less than 0.4 v. if the h2x rising edge comes too soon then there may be some backwards flow of charge for signals above 10,000 electrons. figure 16. charge packet transfer sequence through the floating gate amplifier floating gate amp channel potential vdd1 a b c d v ref vout1 rg1 h1s h2s h2x og1 h1s h2l note: the blue and green rectangles represent two separate charge packets. the direction of charge transfer is from right to lef t.
kae?02150 www.onsemi.com 21 figure 17. timing signals that control the transfer of charge through the floating gate amplifier a b c d h1s h2s h2x rg1 vout1 10% 90% 50% 50% 10% the charge packet is transferred under the floating gate on the falling edge of h2l. when this transfer takes place the floating gate is not connected to any voltage source. the presence of charge under the gate causes a change in voltage on the floating gate according to v = q / c , where q is the size of the charge packet and c is the capacitance of the floating gate. with an output sensitivity of 6.2 v/e ? , each electron on the floating gate would give a 6.2 v change in vout1 voltage. therefore if the decision threshold is to only allow charge packets of 180 electrons or less into the charge multiplier, this would correspond to 180 6.2 = 1.1 mv. if the video output is less than 1.1 mv , then the camera must set the timing of the h2sw2 and h2sw3 pins to route the charge packet to the charge multiplier. this action must take place 28 clock cycles after the charge packet was under the floating gate amplifier. the 28 clock cycle delay is to allow for pipeline delays of the a/d converter inside the analog front end. the timing generator must examine the output of the analog front end and dynamically alter the timing on h2sw2 and h2sw3. to route a charge packet to the charge multiplier (vout3), h2sw2 is held at gnd and h2sw3 is clocked with the same timing as h2s for that one clock cycle. to route a charge packet to the low gain output amplifier (vout2), h2sw3 is held at gnd and h2sw2 is clocked with the same timing as h2s for that one clock cycle.
kae?02150 www.onsemi.com 22 emccd operation figure 18. the charge multiplication process note: charge flows from right to left. a b c d h1bem h2sem h2bem h1sem h1bem h2sem h2bem h1sem channel potential the charge multiplication process , shown in figure 18 above, begins at time step a, when an electron is held under the h1sem gate. the h2bem and h1bem gates block the electron from transferring to the next phase until the h2sem has reached its maximum voltage. when the h2bem is clocked from 0 to 5 v , the channel potential under h2bem increases until the electron can transfer from h1sem to h2sem. when the h2sem gate is above 10 v , the electric field between the h2bem and h2sem gates gives the electron enough energy to free a second electron which is collected under h2sem. then the voltages on h2bem and h2sem are both returned to 0 v at the same time that h1sem is ramped up to its maximum voltage. now the process can repeat again with charge transferring into the h1sem gate. the alignment of clock edges is shown in figure 19. the rising edge of the h1bem and h2bem gates must be delayed until the h1sem or h2sem gates have reached their maximum voltage. the falling edge of h1bem and h2bem must reach 0 v before the h1sem or h2sem reach 0 v. there are a total of 1,800 charge multiplying transfers through the emccd on each quadrant.
kae?02150 www.onsemi.com 23 figure 19. the timing diagram for charge multiplication a b c d h2s 0% 100% h2sem h2bem h1sem h1bem 0% 100% the amount of gain through the emccd will depend on temperature and h1sem and h2sem voltage as shown in figure 20. gain also depends on substrate voltage, as shown in figure 21, and on the input signal, as shown in figure 22. figure 20. the variation of gain vs. emccd high voltage and temperature gain emccd voltage 12.0 0 10 100 12.5 13.0 13.5 14.0 14.5 15.0 15.5 note: this figure represents data from only one example image sensor, other image sensors will vary.
kae?02150 www.onsemi.com 24 figure 21. the change in the required emccd voltage for a gain of 20x vs. the substrate voltage emccd voltage for 20x gain vsub (v) 6 14.2 78910111213 14.4 14.6 14.8 15.0 15.2 15.4 t = 0 c note: this figure represents data from only one example image sensor, other image sensors will vary. figure 22. emccd gain vs. input signal emccd gain input signal (e) 0 16 note: the emccd voltage was set to provide 20x gain with an input of 180 electrons. 17 18 19 20 21 22 50 100 150 200 250 300 if more than one output is used, then the emccd high level voltage must be independently adjusted for each quadrant. this is because each quadrant will require a slightly different voltage to obtain the same gain. in addition, the voltage required for a given gain differs unpredictably from one image sensor to the next, as in figure 23. because of this, the gain vs . voltage relationship must be calibrated for each image sensor, although within each quadrant, the h1sem and h2sem high level voltage should be equal.
kae?02150 www.onsemi.com 25 figure 23. an example showing how two image sensors can have different gain vs. voltage curves gain h1sem, h2sem high level (v) 9 1 10 11 12 13 14 15 10 100 the effective output noise of the image sensor is defined as the noise of the output signal divided by the gain. this is measured with zero input signal to the emccd. figures 24 and 25 show the emccd by itself has a very low noise that goes as the noise at gain = 1 divided by the gain. the emccd has very little clock-induced charge and does not require elaborate sinusoidal waveform clock drivers. simple square wave clock drivers with a resistor between the driver and sensor for a small rc time constant are all that is needed. however, the pixel array may acquire spurious charge as a function of vccd clock driver characteristics. also, the vccd is sensitive to hot electron luminescence emitted from the output amplifiers during image readout. these two factors limit the noise floor of the total imaging array. figure 24. emccd output noise vs. emccd gain in single output mode at ?50 to 22 c 1 0.01 effective noise (e) gain 10 100 0.1 1 10 note: this figure represents data from only one example image sensor, other image sensors will vary.
kae?02150 www.onsemi.com 26 figure 25. emccd output noise vs. emccd gain in quad output mode at ?50 to 22 c 1 0.01 effective noise (e) gain 10 100 0.1 1 10 note: this figure represents data from only one example image sensor, other image sensors will vary. because of these pixel array noise sources , it is recommended that the maximum gain used be 40x at 0 c, which typically gives a noise floor between 1e and 0.4e. using higher gains will provide limited benefit and will degrade the signal to noise ratio due to the emccd excess noise factor. furthermore, the image sensor is not limited by dark current noise sources when the temperature is below 25 c. therefore, cooling below 25 c will not provide a significant improvement to the noise floor. lower temperatures will reduce the number of hot pixel defects observed only during image integration times longer than 1 s. note the useful plot below: figure 26. gain vs. voltage with maximum recommended operating gains marked 13.0 gain emccd voltage 14.0 15.5 1 10 100 1,000 13.5 15.0 14.5 caution: the emccd should not be operated near saturation for an extended period, as this may result in gain aging and permanently reduce the gain. it should be noted that device degradation associated with gain aging is not covered under the device warranty.
kae?02150 www.onsemi.com 27 choosing the operating temperature the reasons for lowering the operating temperature are to reduce dark current noise and to reduce image defects. the average dark signal from the vccd and photodiodes must be less than 1e in order to have a total system noise less than 1e when using the emccd. figures 27 and 28 illustrate how the amount of dark signal in the vccd is dependent on both temperature and voltage, and may be used to choose the operating temperature and vccd clock low level voltage. when operating in quad output mode at 0 c either ?6 v or ?8 v may be used for the vccd clock low level voltage because the dark signal will be equal. but if the operating temperature is ?20 c then the vccd clock low level voltage should be set to ?6 v for the lowest vccd dark signal. for single output mode, the vccd clock low level voltage should be set to ?6 v for temperatures of ?10 c or lower and ?8 v for temperatures of ?10 c or higher. figure 27. dark signal from vccd in quad and single output modes ?50 average dark signal (e) note: both are for a hccd frequency of 20 mhz. the vccd low level voltage is shown for each curve. 0.0 temperature ( c) ?40 ?30 ?20 ?10 0 10 20 0.2 0.4 0.6 0.8 1.0 figure 28. dark signal from vccd in dual output mode at hccd frequency 20 mhz ?50 average dark signal (e) 0.0 temperature ( c) ?40 ?30 ?20 ?10 0 10 20 0.2 0.4 0.6 0.8 1.0 the reason for the different temperature dependencies with the vccd low level voltage at ?6 v vs. ?8 v is spurious charge generation (sometimes called clock - induced char ge). when the vccd low level is at ?8 v , the vccd is accumulated with holes , which reduces the rate of dark current signal generation. however, the amount of clock induced charge is greater. at vccd low level of ?6 v , the vccd is no longer accumulated with holes. so, clock-induced charge generation is less, but dark current is increased.
kae?02150 www.onsemi.com 28 in quad output mode , the clock induced charge generated and the dark current signal are equal at t = 0 c. below t=0 c , the dark current signal is smaller than the clock induced charge , so ?6 v is the best voltage. above t = 0 c , the dark current signal dominates , and ?8 v is the best voltage. the dark signal stops decreasing below t = ?20 c because the vccd is detecting hot electron luminescence from the output amplifiers during image readout. in addition to dark noise, image defects also impact the optimum operating temperature. although the average photodiode dark current is negligible at temperatures below 20 c, as shown by figure 29, the number of photodiode hot-pixel defects is a function of temperature and will decrease with lower temperature. figure 29. photodiode dark current vs. temperature ?30 average pd dark current (e/s) 0.0001 temperature ( c) 0.0010 0.0100 0.1000 ?20 ?10 0 10 20 note that the preceding figures are representative data only, and are not intended as a defect specification. choosing the charge switch threshold the floating gate output amplifier (vout1) is used to decide the routing of a pixel at the charge switch. pixels with large signals should be routed to the normal floating diffusion amplifier at vout2. pixels with small signals should be routed to the emccd and vout3. the routing of pixels is controlled by the timing on h2sw2 and h2sw3. the optimum signal threshold for that transition between vout2 and vout3 is when the signal to noise ratio (s/n) of vout2 is equal to the s/n of vout3. this signal is given by s 2 t g 1 g (eq. 1) where g is the emccd gain, s is the signal level, and t is the total system noise on vout2 in the dark. for values of g greater than 10 , the optimum signal threshold occurs when then signal equals the square of the total system noise floor t . depending on the skill of the camera designer, t will range from 8 to 12 e ? . if the camera has a total system noise of 10 e ? , then the threshold should be set to 100 e ? . however, the floating gate amplifier noise is approximately 60 e?, and so would dominate, making it preferable to set the threshold to at least 3 times the floating gate amplifier noise, or 180 e ? . sending signals larger than 180 e ? into the emccd will produce images with lower s/n than if they were read out of the normal floati ng diffusion output of vout2. see application note and9244. temperature diode there is a diode integrated on the same silicon die as the image sensor that can be used to assist temperature regulation. it is not accurate enough to provide a calibrated temperature value, but it can be used to maintain a constant temperature. the temperature is sensed by forward biasing the diode with 50 a of current and measuring the resulting voltage drop. the current value most preferred is 50 a. it is recommended that it not be less than 40 a or more than 60 a. the primary source of inaccuracy in temperature measurement is noise contributed by other clock inputs to the image sensor. the small amount of coupling of the other clocks to the temperature diode is rectified by the temperature diode and causes an offset error in the voltage reading. the magnitude of the of fset error is dependent upon factors such as the number of outputs used, and the layout of the camera circuit board. while the error frustrates obtaining
kae?02150 www.onsemi.com 29 an accurate absolute temperature value, it is expected to be constant and allow the diode to be used for maintaining a constant temperature. figure 30 shows the forward biased voltage drop across the diode vs. temperature with a current of 50 a. there are two curves showing the offset error. one curve shows the temperature dependence with all image sensor clocks stopped, and the second with all clocks operating at 20 mhz, the offset between the clocks-on and clocks-off curves will be different for every camera design. figure 30. voltage drop across temperature sensing diode with current of 50 a note: the ?clocks on? voltage curve will vary significantly from one camera design to the next. diode voltage (v) temperature ( c) ?50 ?0.85 ?40 ?30 ?20 ?10 0 10 20 30 40 50 ?0.80 ?0.75 ?0.70 ?0.65 ?0.60 ?0.55
kae?02150 www.onsemi.com 30 timing diagrams pixel timing figure 31. pixel timing pattern p1 h2s, h2l h1s h2x rg1 rg2 h2sem h2bem h1sem h1bem 50 ns note: the minimum time for one pixel is 50 ns.
kae?02150 www.onsemi.com 31 black clamp, vout1, vout2, and vout3 alignment at line start the black level clamp should start 3 clock cycles into the line and be active for 28 clock cycles of each row. the first photoactive pixel will arrive at the vout1 (floating gate) output after 34 clock cycles. the first photoactive pixel will arrive at either the vout2 or vout3 after 68 clock cycles, depending on the timing of h2sw2 and h2sw3. when in dual or quad output mode, each row must have exactly 1,036 hccd clock cycles. the pixels arrive at vout3 on the same clock cycle and exactly two rows after they would have arrived at vout2.changing the number of hccd clock cycles with introduce an offset between when pixels arrive at vout2 or vout3. when in single mode, each row must have exactly 2,072 hccd clock cycles. the pixels arrive at vout3 on the same clock cycle and exactly one row after they would have arrived at vout2.changing the number of hccd clock cycles with introduce an offset between when pixels arrive at vout2 or vout3. figure 32. video output at each line start 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 black clamp h2l vout1 vout2, vout3 1036 h2l clock cycles 28 pixels 34 pixels 68 pixels active pixel 1 active pixel 1 time ( s) h2l, vout1, vout2, and vout3 alignment at end of line the last active pixel (the center column of the image), arrives at vout2 or vout3 on the 1,036 th clock cycle of the hccd. the last photoactive pixel arrives at vout1 34 clock cycles before vout2 or vout3. when in single output mode, the pixels arrive at vout3 one line delayed from when they would have arrived at vout2. when in dual or quad output modes, the pixels arrive at vout3 two lines delayed from when they would have arrived at vout2. figure 33. video output at end of each line for dual or quad output modes time ( s) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 h2l vout1 vout2, vout3 h2l clock cycle 1036 34 pixels active pixel 968 active pixel 968
kae?02150 www.onsemi.com 32 vccd timing table 15. timing definitions symbol note minimum nominal maximum units t va vccd transfer time a 0.46 0.50 0.50 s t vb vccd transfer time b 0.46 1.30 7.50 s t sub electronic shutter pulse 1.0 1.5 10.0 s t 3 photodiode to vccd transfer time 1.0 1.5 5.0 s v1, v2, v3, v4 alignment figure 34. timing pattern f1. vccd frame timing to transfer charge from photodiodes to the vccd when using the bottom hccd, outputs a or b v1b, v1t t va v2b, v4t v3b, v3t v4b, v2t t vb t 3 t vb t vb t vb t vb t va t va t va figure 35. timing pattern f2. vccd frame timing to transfer charge from photodiodes to the vccd when using all four outputs in quad mode v1b t va v2b, v3t v3b, v4t v4b t vb t 3 t vb t vb t vb t vb t va t va t va v1t v2t
kae?02150 www.onsemi.com 33 figure 36. line timing l1. vccd line timing to transfer one line of charge from vccd to the hccd when using the bottom hccd, outputs a or b in single or dual output modes v1b, v1t t va v2b, v4t v3b, v3t v4b, v2t t vb t vb t vb t vb t va t va t va figure 37. line timing l2. vccd line timing to transfer one line of charge from vccd to the hccd when using all four outputs in quad mode v1b, v2t t va v2b, v3t v3b, v4t v4b, v1t t vb t vb t vb t vb t va t va t va
kae?02150 www.onsemi.com 34 electronic shutter figure 38. electronic shutter timing pattern s1 vsub t vb hccd vccd v ab 3.3 v 0 v 0 v ?8 v v ab + v es t sub first vccd clock edge last hccd clock edge t vb caution: do not clock the emccd register while the electronic shutter pulse is high. figure 39. the state of the hccd and emccd clocks during the frame, line, and electronic shutter timing sequences clock state h1s high h2s low h2sw low h2l low h2x low h1sem high h1bem high h2sem low h2bem low
kae?02150 www.onsemi.com 35 hccd timing to reverse the direction of charge transfer in a horizontal ccd , exchange the timing pattern of the h1b and h2b inputs of that hccd. if a hccd is not used, hold all of its gates at the high level. when operating in single or dual output modes, the vdd23cd, vdd1c, and vdd1d amplifiers must still be powered. the outputs vout1, vout2, and vout3 for quadrants c and d may be left unloaded. table 16. hccd timing mode hccd a, b timing hccd c, d timing single h1ba = h2bb = h1sa = h1sb h2ba = h1bb = h2sa = h2sb 3.3 v dual h1ba = h1bb = h1sa = h1sb h2ba = h2bb = h2sa = h2sb 3.3 v quad h1ba = h1bb = h1sa = h1sb h2ba = h2bb = h2sa = h2sb h1bc = h1bd = h1sc = h1sd h2bc = h2bd = h2sc = h2sd image exposure and readout the flowchart for image exposure and readout is shown in figure 40. the electronic shutter timing may be omitted to obtain an exposure time equal to the image read out time. nexp is the number of lines exposure time and nv is the number of vccd clock cycles (row transfers). table 17. image exposure and readout mode nh nv line timing frame timing pixel timing single 2,072 1,124 l1 f1 p1 dual 1,036 562 l1 f1 p1 quad 1,036 562 l2 f2 p1 figure 40. the image readout timing flow chart frame timing line timing pixel timing repeat nh times repeat nv ? nexp times electronic shutter timing repeat nexp times line timing pixel timing repeat nh times
kae?02150 www.onsemi.com 36 long integrations and readout for extended integrations the output amplifiers need to be powered down. when powered up, the output amplifiers emit near infrared light that is sensed by the photodiodes. it will begin to be visible in images of 30 second integrations or longer. to power down the output amplifiers set vdd1 and vss1 to 0 v , and vdd23 to +5 v. do not set vdd23 to 0 v during the integration of an image. during the time the vdd2 supply is reduced to +5 v the substrate voltage reference output subv will be invalid. for cameras with long integration times, the value of subv will have to digitized by and adc and stored at the time when vdd23 is +15 v. the sub pin voltage would be set by a dac. the hccd and emccd may be continue to clock during integration. if they are stopped during integration then the emccd should be re-started at +7 v to flush out any undesired signal before increasing the voltage to charge multiplying levels. the timing flow chart for long integration time is shown in figure 41 . figure 41. timing flow chart for long integration time stop all vccd clocks at the v low (?8 v) level. pulse the electronic shutter on vsub to empty all photodiodes. integration begins on the falling edge of the electronic shutter pulse. set vdd23 = +5.0 v set vdd1 = 0.0 v set vss1 = 0.0 v wait ? set vdd23 = +15.0 v set vdd1 = +5.0 v set vss1 = ?8.0 v begin normal line timing readout the photodiodes and one image. repeat for at least 2,048 lines in single or dual output mode, 1,024 lines in quad output mode.
kae?02150 www.onsemi.com 37 storage and handling table 18. storage conditions description symbol minimum maximum units notes storage temperature t st ?55 80 c 1 humidity rh 5 90 % 2 1. long-term storage toward the maximum temperature will accelerate color filter degradation. 2. t = 25 c. excessive humidity will degrade mean time to failure (mttf). for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on environmental exposure, please download the using interline ccd image sensors in high intensity lighting conditions application note (and9183/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kae?02150 www.onsemi.com 38 mechanical information pga completed assembly figure 42. completed assembly (1/2) 1. substrate is a 141-pin ceramic pga package. 2. body is black alumina. 3. pins are kovar or equivalent, plated with 1.00 microns of gold over 2.00 microns of nickel. 4. wire is wedge bonded aluminum (1% si). 5. ablebond 967?1 epoxy for die attach. 6. no materials to obstruct the clearance through the package holes. 7. exposed metal is 1.00 micron minimum gold over 2.00 micron minimum nickel. 8. glass lid is schott e263teco, n d 1.5231. thickness 0.76 0.05 mm. 9. recommended mounting screws: 1.6 0.35 mm (iso standard), 0?80 (unified fine thread standard). notes:
kae?02150 www.onsemi.com 39 figure 43. completed assembly (2/2) 1. die is standard thickness for 150 mm silicon wafer: 0.675 0.020 mm. 2. singulated die is approximately 12.910 8.500 mm, for a 50 micron saw kerf. 3. the optical center of the image area is at the center of the die and the center of the package. notes:
kae?02150 www.onsemi.com 40 pga clear cover glass figure 44. pga clear cover glass 1. dust and scratch: 10 micron maximum (?a? zone) 2. glass material: schott d263t eco notes: on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 kae?02150/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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